1. Overview of the board
XC7Z100+AD9361 based on dual-receive dual-transmit radio frequency board is based on Xilinx ZYNQ FPGA and ADI wireless transceiv chip AD9361 developed special function board, used in 4G small base station, wireless image transmission, data transceiv and other fields.
2. Board principle and function
The board uses the XC7Z100 as the main processor, including the embedded processing of Dual ARM Cortex-A9 core processor, 32-bit 1GB DDR3 storage at the PS end, 1 RS232 interface, 1 USB interface, and 1 10-100-1000 network interface. PS end QSPI flash storage, PS end SD card, Emmc storage; The PL side has 2GB capacity DDR3 storage, the PL side expands HDMI output for video display applications, and the PL side expands 9 channels of I/O and 4 LED indicators.
The PL-end extends the AD9361 chip, a highly integrated radio frequency (RF), agile transceiver that provides dual-channel transmitters and receivers, an integrated frequency synthesizer, and digital signal processing capabilities. This IC has a diversified combination of high performance and low power consumption, FMC sub-card for 2 input, 2 output RF transceiver card, with FPGA work to meet the 3G, 4G macro cellular time division duplex (TDD) and frequency division duplex (FDD) base station application requirements.
- 32-bit 1GB DDR3 storage on the PS server
- RS232 ports used by PS
- PS USB port
- PS uses one 10-100-1000 Mbps Ethernet (RGMII) network port
- PS QSPI flash storage
- SD card on PS, Emmc storage
- PL provides 32bit DDR3 storage with 1GB capacity
- PL extension HDMI output for video display applications
- PL terminal extends 16 I/ OS and 4 LED indicators
- Add one 10 Gbit/s SFP+ optical port to PL
Board simulation interface:
- Dual reception: RX1, RX2; Dual transmission: TX1, TX2; External local oscillator interface: EXT_LO; External clock reference: REF_CLK_IN
- RF 2x2 transceiver with integrated 12-bit DAC and ADC
- TX band: 47 MHz to 6.0 GHz
- RX band: 70 MHz to 6.0 GHz
- Supports TDD and FDD operations
- Tunable channel bandwidth: <200 kHz to 56 MHz
- Dual channel receiver: 6-way differential or 12-way single-ended input
- Excellent receiver sensitivity with a noise figure of 2 dB (800 MHz LO)
- RX gain control
Real-time monitoring and control signals for manual gain
Independent automatic gain control
- Dual transmitter: 4 differential outputs
- high linearity broadband transmitter
TX EVM:
≤−40 dB
TX noise:
≤−157 dBm/Hz Background noise
TX monitor: Dynamic range
≥66 dB, accuracy =1 dB
- integrated decimal N fraction frequency synthesizer
- 2.4Hz Maximum local oscillator (LO) step板卡性能指标：
| |
No. |
Items |
Specifications |
Remark |
| Tx |
1 |
Frequency |
70~6000MHz |
|
| 2 |
Bandwidth |
Up to 56 MHz |
real-time bandwidth, tunable |
| 3 |
Transmission |
>5dBm |
CW |
| 4 |
EVM |
<1.5% |
Typical:5dBm @20MHz bandwidth |
| 5 |
Gain Control Range |
>80dB |
|
| 6 |
Gain Step |
0.25 dB |
|
| 7 |
ACLR |
< -45dBc |
@ 0dBm LTE output |
| 8 |
Spurious |
TBD |
|
| 9 |
SSB Suppression |
35dBc |
|
| 10 |
LO Suppression |
50dBc |
|
| 11 |
DAC Sample Rate (max) |
61.44MS/s |
|
| 12 |
DAC Resolution |
12bits |
|
| |
| Rx |
1 |
Frequency |
70~6000MHz |
|
| 2 |
Bandwidth |
Up to 56 MHz |
real-time bandwidth, tunable |
| 3 |
Sensitivity: |
-90dBm@20MHz |
Noise Figure < 8dB |
| 4 |
EVM |
<1.5% |
@ -30dBm input |
| 5 |
Gain Control Range |
>60dB |
|
| 6 |
Gain Step |
1dB |
|
| 7 |
Blocking |
TBD |
|
| 8 |
Noise Figure |
<8dB |
Maximum RX gain |
| 9 |
IIP3 (@ typ NF) |
-25dBm |
|
| 10 |
ADC Sample Rate (max) |
61.44MS/s |
|
| 11 |
ADC Resolution |
12bits |
|
| 12 |
ADC Wideband SFDR |
78dBc |
|
| |
1 |
Voltage |
3.3V |
|
| 2 |
ON/OFF TIME |
<6uS |
For TDD model |
| 3 |
Duplexing Model |
TDD or FDD |
|
| |
4 |
W/ GPSDO Reference |
0.01ppb |
|
Physical characteristics
Dimensions: 120x162.4mm;
Working temperature: industrial grade -40℃ ~ +85℃
3. Software system
Refer to ADI development board website full set of software, firmware program chip XC7Z100.
The ARM linux software is identical to the client software.
Customer development mainly considers LibIIO API applications, client applications, or firmware programs to modify the logic code of the PL side and insert personalized algorithm applications. The functional architecture of LibIIO API is shown in Figure 6 below.
Figure 6 LibIIO API functional architecture diagram
As above, steps 2,3 build the Ubuntu software runtime environment within the ZYNQ-7000 SOC. Image files include u-boot, kernel, device tree, and file system.
https://wiki.analog.com/resources/tools-software/linux-software/iio_oscilloscope
Software execution:
Data output, output support single frequency, multi-frequency and arbitrary waveform
